As processors have continued to advance in performance at a rampant pace, DRAM-based memory systems have largely not been able to keep up. Various efforts have been made to improve both the speed of the memory cells making up DRAM components and to improve the apparent speed of access to arrays of DRAM components by accessing arrays with ever wider memory busses. However, wider busses require greater quantities of electrical connections, i.e., a wider memory, to transfer data, so more recent efforts have focused on providing memory buffer logic that provides a wider memory bus connecting to the memory devices of a memory array, but which converts from that wider memory bus to a narrower memory bus that may be connected to other components of a memory system (e.g., a memory controller, or memory buffer logic connected to other memory arrays) so that such other components need not be designed to support a connection to as wide a memory bus.
To keep pace with data throughput made possible with the ever wider buses connecting to the memory devices of memory arrays, a form of memory buffer logic has been considered employing narrow memory buses connecting to other memory system components in point-to-point buses (i.e., a “daisy chain” topology of bus connections), rather than the more widely used multi-drop topology, to better support differential signaling and other techniques to allow for higher transfer rates.
Unfortunately, the use of such a combination of memory buffer logic and point-to-point buses adds difficulties to development and test efforts. The fact that a conversion takes place between a wider bus and a narrow bus for every memory array that is provided in a memory system requires that provision be made for testing such conversions. Also, the use of point-to-point buses often requires the monitoring of signals across such point-to-point buses to be accomplished by breaking into the point-to-point connections to carry out testing.